23
9152BINDCO02/10
ATA8743
12. CPU Core
12.1 Overview
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
12.2 Architectural Overview
Figure 12-1. Block Diagram of the AVR Architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture with
separate memories and buses for program and data. Instructions in the Program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the Program memory. This concept enables instructions to be executed
in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Interrupt
Unit
Watchdog
Timer
Analog
Comparator
Timer/Counter 0
Timer/Counter 1
Universal
Serial Interface
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相关PDF资料
ATAVRRZ200
KIT DEMO AT86RF230
AV101-12LF
ATTENUATOR HIP3 0.70-1GHZ 8-SOIC
AV102-12LF
ATTENUATOR HIP3 1.7-2GHZ 8SOIC
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XFRMR BALUN RF 200-500MHZ 1608
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